1. Field of the Invention
The present invention relates to microprocessors, and in particular to a microprocessor having registers accessible by a programmable logic device.
2. Description of the Related Art
Microprocessors are well known in the art. FIG. 1 illustrates a conventional configuration of a computer 100 having a microprocessor which includes an arithmetic logic unit (ALU) block 101 and a control unit 103. ALU block 101 manipulates data provided by input/output (I/O) device 102 and memory 104. I/O device 102 communicates with a user or a peripheral device (neither shown in FIG. 1) via output bus 109A and input bus 109B. In one computer, I/O device 102 communicates with a keyboard or a field programmable gate array (FPGA)(described in further detail in reference to FIG. 3). Memory 104 typically includes nonvolatile memory cells, such as electrically programmable read only memory (EPROM) cells for storing the computer program, and volatile memory cells, such as random access memory (RAM) cells for providing storage for data generated by ALU block 101. Control unit 103, relying on instructions provided in the computer program, controls the operation of ALU block 101, memory 104, and I/O device 102 via buses 111A/111B, 105A/105B, and 108A/108B, respectively.
Referring to FIG. 2, ALU block 101 typically includes an ALU 112, a register file 114, multiplexer 121, and latches 113A, 113B, and 113C. An address from controller 103 (not shown) on bus 111A is provided to an input port 115A of register file 114, thereby selecting an output signal YA at a clock signal. Similarly another address from controller 103 on bus 111B is also provided to an input port 115B of register file 114, thereby selecting a second output signal YB at the same clock signal. In this manner, output signals YA and YB are provided simultaneously at the output ports of register file 114 on output lines 118A and 118B, respectively. Latches 113A and 113B are coupled between output lines 118A and 118B, respectively, and ALU 112. Thus, latches 113A and 113B, which continuously sample their input signals and change their output signals in response to their input signals independent of the clock signal provided to register file 114 in their enabled state, transfer output signals YA and YB to ALU 112. Multiplexer 121 is programmed to transfer either the output signal from ALU 112, the output signal from memory 104 via line 106A, or the output signal from I/O device 102 via line 107B to latch 113C. Latch 113C provides output signals to I/O device 102 and memory 104 on buses 107A and 106B, respectively. Note that latch 113C also typically provides a buffered feedback signal via buffer 120 on line 119 to a data input port DIN of register file 114.
In a conventional reduced instruction set computer (RISC) processor, an operation requires three machine operating cycles (hereinafter referred to as periods). These periods are Read, ALU Operating, and Write periods. For example, during the Read period, control unit 103 (FIG. 1) retrieves an instruction from memory 104 and transfers the address portions of that instruction to register file 114 (FIG. 2) via bus 111A or bus 111B to retrieve operands on output lines 118A/118B. During the ALU operating period, the operation designated by the instruction is performed in ALU 112. Finally, during the Write period, the result is stored in register file 114 via feedback line 119 and data input port DIN. Note that the data write address is included as part of the instruction and is typically saved until needed.
The Read, ALU Operating, and Write periods are overlapping. For example, a register may perform a Write operation in one-half of one period and perform a Read operation in the other half of that period. It logically follows that periods do not correspond to specific clock cycles. Addresses are provided on buses 111A or 111B from control unit 103 as necessary.
One typical instruction to register file 114 is to add the value in a first register to the value in a second register (neither register shown), and then put the result of this summation into the second register of register file 114. In this manner, ALU block 101 operates as an accumulator. Alternatively, the value in latch 113C is written to a I/O device 102, such as an FPGA, via output bus 107A. Thus, one instruction is required to move the data, whereas another instruction is required to retrieve the result, thereby introducing considerable delay in the microprocessor and I/O device interface.
Therefore, a need arises for a structure which minimizes instructions and associated delay in the interface between the microprocessor and the I/O device.